With out DMA, when the CPU is utilizing programmed enter/output, it is usually totally occupied for your complete duration of the read or write operation, and is thus unavailable to perform different work. With DMA, the CPU first initiates the switch, then it does other operations whereas the transfer is in progress, and it lastly receives an interrupt from the DMA controller (DMAC) when the operation is done. This feature is helpful at any time that the CPU can't sustain with the speed of data transfer, or when the CPU must perform work whereas ready for a relatively gradual I/O information transfer. Many hardware systems use DMA, together with disk drive controllers, graphics playing cards, community playing cards and sound cards. DMA can also be used for intra-chip data switch in some multi-core processors. Computers that have DMA channels can switch knowledge to and from units with a lot much less CPU overhead than computers without DMA channels. Equally, a processing circuitry inside a multi-core processor can transfer information to and from its native memory without occupying its processor time, permitting computation and data transfer to proceed in parallel.

DMA can also be used for "memory to memory" copying or shifting of knowledge within memory. DMA can offload costly memory operations, such as giant copies or scatter-collect operations, from the CPU to a dedicated DMA engine. An implementation instance is the I/O Acceleration Expertise. DMA is of interest in community-on-chip and in-memory computing architectures. Standard DMA, additionally known as third-occasion DMA, uses a DMA controller. A DMA controller can generate memory addresses and provoke memory read or write cycles. It comprises several hardware registers that can be written and browse by the CPU. These include a memory handle register, a byte rely register, and a number of control registers. Depending on what features the DMA controller offers, these management registers might specify some mixture of the source, the destination, the direction of the switch (studying from the I/O system or MemoryWave writing to the I/O system), the dimensions of the transfer unit, and/or the number of bytes to transfer in a single burst.

To perform an enter, output or Memory Wave memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of phrases to switch, and the memory address to make use of. The CPU then commands the peripheral device to provoke an information transfer. The DMA controller then offers addresses and browse/write control lines to the system memory. Each time a byte of information is able to be transferred between the peripheral device and memory, the DMA controller increments its inner tackle register until the full block of knowledge is transferred. Some examples of buses utilizing third-party DMA are PATA, USB (earlier than USB4), MemoryWave and SATA